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This article will demonstrate how to convert phase noise into jitter so that the SNR degradation can be easily calculated. A low aperture jitter specification of an ADC is critical to achieving high levels of signal-to-noise ratios (SNR). The sampling process is basically a multiplication of the sampling clock and the analog input signal. Note that the phase noise curve is somewhat analogous to the input voltage noise spectral density of an amplifier. We have seen that oscillators are typically specified in terms of phase noise, but in order to relate phase noise to ADC performance, the phase noise must be converted into jitter. It should be noted that computer programs and spreadsheets are available online to perform the integration by segments and calculate the rms jitter, thereby greatly simplifying the process (References 8, 9).
Crystal oscillators generally offer the lowest possible phase noise and jitter, and some examples are shown for comparison in Figure 6. Figure 6: 100-MHz oscillator broadband phase noise floor comparisons (Wenzel ULN and sprinter series specifications and pricing used with permission of Wenzel). Figure 7: Jitter calculations for low noise 100-MHz crystal oscillators (phase noise data used with permission of Wenzel Associates). In system designs requiring low jitter sampling clocks, the costs of low-noise-dedicated crystal oscillators is generally prohibitive. Figure 8: Using a phase-locked loop (PLL) and bandpass filter to condition a noisy clock source.
Analog Devices offers a wide portfolio of frequency synthesis products, including DDS systems, N, and fractional-N PLLs.
Historically, PLL design relied heavily on textbooks and application notes to assist in the design of the loop filter, etc. Although not as good as relatively expensive stand-alone crystal oscillators, modern PLLs using crystal VCOs (along with suitable filtering) can achieve jitter performance suitable for all but the most demanding requirements. The entire problem of clock distribution has become much more critical because of low jitter requirements. Flicker noise occurs in almost all electronic devices, and it has a variety of different causes, although these are usually related to the flow of direct current.
It is important in many areas of electronics including within oscillators used as RF sources. Flicker noise occurs in virtually all electronic components (as well as in many other physical items in everyday life from the earth's rotation to undersea currents and many other items).
Often, Flicker noise is mentioned in relation to semiconductor devices such as transistors and especially MOSFET devices. As flicker noise is proportional to the inverse of the frequency, in many applications of electronics components such as within RF oscillators there are regions in which the flicker noise dominates and other regions where the white noise from sources such as shot noise and thermal noise dominate.

Within the oscillator the flicker noise manifests itself as sidebands that are close to the carrier, the other forms of noise extending out from the carrier with a flatter spectrum, although decaying the greater the offset from the carrier.
In view of this, there is a corner frequency, fc, between the regions dominated by the different forms of noise.
For a system such as an oscillator it is generally found that the noise outside that where the flicker noise predominates is phase noise.
MOSFETs have a higher fc (can be in the GHz range) than JFETs or bipolar transistors which is usually below 2 kHz for the latter. Although the relationship between SNR and jitter is well known, most oscillators are specified in terms of their phase noise. This is multiplication in the time domain, which is equivalent to convolution in the frequency domain. In order to make the graph relevant to modern ADC applications, the oscillator frequency (sampling frequency) is chosen to be 100 MHz for discussion purposes, and a typical graph is shown in Figure 4. The curve is broken into a number of individual areas (A1, A2, A3, A4), each defined by two data points. The wisest approach is to integrate each area separately as explained below and examine the magnitude of the jitter contribution of each area.
In each case, the data points were taken directly from the manufacturer’s data sheet. Rohde, Digital PLL Frequency Synthesizers, Theory and Design, Prentice-Hall, 1983, ISBN 0-13-214239-2, all of Chapter 2 and pp. A number of techniques are being used by attackers, but are the security experts ahead of the game. ADCs are available with aperture jitter specifications as low as 60-fs rms (AD9445 )14-bits at 125 MSPS and AD9446 16-bits at 100 MSPS).
Therefore, the spectrum of the sampling clock oscillator is convolved with the input and shows up on the FFT output of a pure sinewave input signal (see Figure 2). There are also regions where x = 2, 3, 4, and these regions occur progressively closer to the carrier frequency. Notice that the phase noise curve is approximated by a number of individual line segments, and the end points of each segment are defined by data points.
Generally speaking, the upper frequency range for the integration should be twice the sampling frequency, assuming there is no filtering between the oscillator and the ADC input. In practice, however, the oscillator specifications generally will not be given for offset frequencies less than 10 Hz, or so—however, this will certainly give accurate enough results in the calculations. The low frequency contributions may be negligible compared to the broadband contribution if a crystal oscillator is used. The two Wenzel oscillators are fixed-frequency and represent excellent performance (Reference 9).

There are many good references on PLL design (see References 10-13), and we will not pursue that topic further, other than to state that using a narrow bandwidth loop filter in conjunction with a voltage-controlled crystal oscillator (VCXO) typically gives the lowest phase noise. With a 10-kHz bandwidth loop filter, the phase noise of the ADF4360-1 2.25-GHz PLL is shown in Figure 10, and the line-segment approximation and jitter calculations shown in Figure 11. To start, choose a circuit by entering the desired output frequency range, and select a PLL, VCO, and a crystal reference. This article has shown how to convert phase noise into jitter so that the SNR degradation can be easily calculated. Best, Phase-Locked Loops: Theory, Design and Applications, Fourth Edition, McGraw-Hill, 1999, ISBN 0071349030.
Extremely low jitter sampling clocks must therefore be utilized so that the ADC performance is not degraded, because the total jitter is the root-sum-square of the internal converter aperture jitter and the external sampling clock jitter. Phase noise is defined as the ratio of the noise in a 1-Hz bandwidth at a specified frequency offset, fm, to the oscillator signal amplitude at frequency fO.
A lower frequency of integration of 100 Hz is reasonable in most cases, if that specification is available.
Other types of oscillators may have significant jitter contributions in the low frequency area, and a decision must be made regarding their importance to the overall system frequency resolution.
It is difficult to achieve this level of performance with variable frequency signal generators, as shown by the –150 dBc specification for a relatively high quality generator.
Once the loop filter configuration has been selected, the circuit can be analyzed and optimized for phase noise, phase margin, gain, spur levels, lock time, etc., in both the frequency and time domain. However, oscillators used for sampling clock generation are more often specified in terms of phase noise rather than time jitter. In practice, the lower frequency limit of 0.01 MHz can be dropped from the calculation, as it does not affect the final result significantly. For informational purposes, the individual jitter contributions of each area have been labeled separately. Further reduction in the white noise floor can be obtained by following the PLL output with an appropriate bandpass filter.
The program also performs the rms jitter calculation based on the PLL phase noise, thereby allowing the evaluation of the final PLL output as a sampling clock. The purpose of this discussion is to develop a simple method for converting oscillator phase noise into time jitter.

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