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18.08.2014
A 100kHz oscillator within IC1 (UC3524) generates pulses, which are processed by the pulse width modulator (within IC1)used to drive the power switching transistors. The pulse width and therefore the output voltage is controlled by the error amplifier in IC1.
Over current protection is provided to ensure that the supply is shut down in the event of too high a current demand at the output.
Each pulse of current in the power switching transistors produces a voltage pulse across the sensing resistor R12. The push pull switching transistors create an AC waveform across the transformer primary winding, and the secondary winding feeds a conventional full wave rectifier and LC low pass filter to supply the load with a stable 5V at the output terminals. The oscillator within IC1 produces narrow 100kHz (approx) pulses that are used as clock pulses for the Switch Logic within IC1.
The pulse width modulator comprises the comparator within IC1 and the switching logic, which consists of a bistable and two three input NOR gates.
The error amplifier compares a stable reference voltage on pin 1 (set by Vr1 supplied from an internally regulated 5V from pin 16) with a sample of the load voltage developed across the opto-isolator emitter resistor, R11. The facilities of the UC3524 that are used in this circuit are shown in more detail in Fig.
Output Q provides an input to NOR gate a, and output Q (the opposite of Q) provides an input to NOR gates b.
The third input to each of the NOR gates is provided by the comparator output, which is a series of variable width low state pulses, produced by comparing the DC error voltage from the error amplifier in IC1 with the ramp produced by the oscillator timing capacitor C2. As each NOR gate output goes high, only when all of its three input signals are low, alternate high state pulses, whose width depends on the value of the error voltage, are fed to the bases of the internal transistors Qa and Qb. The internal drive transistors Qa and Qb each produces a series of pulses at its collector, and an a series of anti-phase pulses at its emitter. Because the transformer primary centre tap is connected to the main (+VIN) supply, it will always be at the supply potential. Because of the push pull design used by this circuit, it is a simple matter to arrange for such a circuit to have multiple outputs.
The total current supplied to the multiple outputs however, must not exceed the maximum current rating of the SMPS.
Current limiting, which is capable of completely shutting down the circuit under extreme overload conditions is provided by the action of IC2 and the shut down transistor between pins 9 and 10 within IC1. Every time either transistor conducts, the resulting large emitter current produces a voltage pulse across R12.
If the peak voltage of any of these pulses applied to the non-inverting input of IC2 exceeds the stabilised DC voltage at the inverting input, a positive pulse will be produced at the output, and therefore at the base of Qc within IC1. The action of the current limit circuit is not absolutely instant however, due to the presence of C4 on the shut down compensation pin (9) of IC1.
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The circuit uses push pull power switching driving a high frequency transformer, which fully isolates the output circuit from the input. The width of the processed drive pulses controls the length of time for which the power switching transistors conduct, and therefore the amount of power delivered to the transformer.
This measures the difference between a sample of the output voltage, fedback via the opto-isolator, and a reference voltage set by Vr1. The amplitude of these pulses is proportional to the current being delivered to the transformer by the switching circuit. The logic rule for a NOR gate is that its output will be high, only when all its three inputs are low. The lower the value of the error voltage (due to a higher value of "sample" voltage at pin 1) the narrower the pulses produced. The collector voltages of Tr3 and Tr4 will also be at +VIN during the periods when both transistors are turned off. A sample of the load voltage is fed back to the LED within opto-isolator IC3 via the LED current limiting resistor R13. Different (higher or lower) voltages can be obtained by using a transformer similar to the one illustrated in Fig. Each supply line will have its own rectifier and filter system, and may also include some extra point of load regulation. This will cause the collector voltage of this transistor to fall, also reducing the error amplifier output that is controlling the pulse width modulator. This capacitor tends to integrate the voltage changes on the collector of the shut down transistor so that very rapid (cycle by cycle) variations of the output voltage during current limiter action are avoided. If the peak value of any of these pulses exceeds the DC voltage set by Vr2 (Current limit) then the output from IC2 will cause pulse width modulator input to reduce the width of the pulse being produced by the modulator at that time, momentarily reducing the output voltage. The higher the output voltage, the brighter the glow from an LED sealed within the secondary side, and the larger the DC output voltage derived from pin 4 of IC3 in the primary side of the device. The ramp waveform produced as C2 charges is also used as an input to the inverting input of the comparator in IC1.
These narrower pulses, when used to turn on the power switching transistors TR3 and Tr4, will lead to a reduction in power in the transformer and a reduction in load voltage.
A voltage sample will normally be taken from only one of the outputs to provide feedback to the pulse width modulator however, as controlling the power applied to the transformer primary will control all the voltage outputs. This action has the effect of reducing the width of the pulse presently being produced, thus instantly reducing output voltage. If there is a difference, the width of the pulses produced by the pulse width modulator is increased or decreased to correct the error. If the over current condition disappears, the output voltage will be restored to its normal level, but if the load current remains high, the current limiter will continue to reduce the pulse width, dependent on the amount of over current, even down to zero in the case of a short circuit output.
If the current overload disappears, the pulse width modulator will return to normal operation. Go to that page to read the explanation about above power supply related circuit diagram.ads 728-->Switch Mode Voltage Regulator with 85% efficiencySwitch Mode Power Supplies (SMPS) is now widely used in modern electronic equipment due to its compact design and high efficiency of about 80% or more. If not, subsequent pulses will be further reduced until the output voltage falls (if necessary) to zero.



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