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Vicor Corporation introduced its Picor PI33XX Cool-PowerA® ZVS buck regulator series to meet the needs of board-level designers for maximum power density and flexibility for high efficiency point of load DC-DC regulation.
Has Thomas Edison ultimately won the DC vs AC power transmission controversy against Tesla?
The pictures below show some typical waveforms observed at the gates of MOSFETs when driven by gate-drive transformers.
At very high switching frequencies it is possible to make use of the resonance caused by the leakage inductance and MOSFET gate capacitance.
All of the pictures above show waveforms measured at the gate-source terminals of power MOSFETs with the device switching no current. However, it is worth noting that this does not represent the real life situation where the MOSFET is switching considerable power.
Notice how little flat regions form part way up the rising and falling edges of the pulse waveforms. The duration of each plateau region corresponds with how long it takes for the MOSFET to transition through the linear region. As the power supply voltage is increased the gate drive circuit has difficulty overcoming the Miller effect, and these flat regions become progressively longer. From this we can see that to achieve high efficiency, we really need to minimise the duration of these plateau regions.
The point of this discussion is to show that you should really check the MOSFET gate waveforms right at the MOSFET device with some power applied to the bridge circuit.
A more detailed explanation of the Miller effect and MOSFET switching in general can be found in most power electronics books.
Therefore analog signals deteriorate from amplitude distortion that causes extra frequency components. To maintain the digital signal shape the ratio of the amplitudes of these harmonics should be constant and the phase shift between the harmonics (the group delay) should be zero. For an approximate square wave the signal should contain at least the first and third harmonic. As the frequency of the harmonics increase the load may often first be approximated by a resistor, next by a capacitor. To investigate the (digital) signal distortion that a certain physical body (bondwires, PCB tracks, via's etc) causes a 3D EM simulation model can be created that describes the electrical properties like attenuation and phase shift.
The coupling between the lines is due to a partially joint magnetic field, which is modeled by the coupling of the L in a section with the L's in the same section of another line.
Furthermore the charge in the line will influence the charge in another line, which means that the electric fields of a line is coupled to the other lines. The larger the number of sections in a line the better the time delay of a physical line is approached.
First a 3D simulation was done to get a 64-port s-parameters set, each line having two ports, so this set contains 32 coupled two ports. In the next step the K-factors for the L's were calculated and the coupling capacitors were determined. The above figures show a nearly frequency independent behavior of the model parameters over frequency, except for the resistance and conductance. The resistance is important for the Q of the structure and remains difficult in RLGC models.
When properly calculated a RLGC(k) model can accurately model the time behavior of IC packages or bus structures.

The integration of a high performance Zero-Voltage Switching (ZVS) topology within this series increases point of load performance, providing power efficiency up to 98% peak.
Ideally we want the waveform at the gate of a MOSFET to be very clean, with steep rising and falling edges, no overshoot, no ringing, and no droop to the tops and bottoms of the pulses.
This technique is used to good effect in RF amplifiers that operate in the switching mode up to tens of megahertz! The gate drive waveforms actually change slightly when the MOSFET is switching real current. It shows how the gate-drive waveform of one MOSFET in a half-bridge changes as the main high-voltage supply is gradually increased from zero to 400 volts. These plateau regions form because the Miller capacitance tries to hold the gate voltage at the MOSFET's threshold level while the device turns on or off.
Therefore the MOSFET takes longer to transition through the linear region where power dissipation is high, and switching losses increase.
It is also apparent that the overall slope of the rising and falling edges of the gate drive waveform is less important than what happens in the short instant when the MOSFET switches. In many cases it is hard to observe the gate-source waveforms when the bridge circuit is being powered directly from the mains supply.
This is because the Miller effect capacitively couples the drain to the gate of the MOSFET.
The impedance of the capacitance drops with increasing frequency therefore the amplitude of the signal is more reduced and the phase delay is larger. As this effect is less pronounced it is normally sufficient to model it by a coupling capacitor between the line and the neighboring line. For lines up to half a wavelength 1 to 4 sections are often enough to have a sufficient accurate model.
An IC contains a 32 bits bus that is routed via bondwires, tracks and vias to the backside of a BGA package.
In principle all parameters are frequency dependent, but if a transmission line is a good model for the 3D structure the frequency dependency of L, C and K is minimal. Best practice is to choose an appropriate value by comparing the s-parameters of the model and the 3D structure. The next two pictures show the response of the RLGC(k) model in a spice simulation and the response of the 3D structure in a field simulator. Products in the series are highly integrated with control circuitry, power semiconductors and support components in a high density 10mmx14mmx2.56mm LGA System in Package (SiP). Unfortunately, this is rarely the case when gate drive transformers are used, and a number of things can go wrong. There was no voltage applied to the drain terminals of the devices and they were not switching any load current.
This behaviour is due to something called "Miller Capacitance" which exists between the Drain terminal and Gate terminal of a MOSFET.
There are plateaus on both the positive and the negative pulses because two MOSFETs are being driven by one single gate drive transformer.
It is during the switching transitions when most gate drive circuits are stretched to their limits. In cases where the MOSFET switches on with zero voltage across it, the Miller effect is non-existant because there is no drain-source voltage at the switching time. For example in digital signals a voltage above a Vhigh limit would present a one, and below the Vlow limit a zero.

For example analog signals are often defined in the frequency domain, they have a certain power in a frequency band, while the momentary phase, that is the exact phase at time t, is not important.
Hold the mouse over the picture on the right to see the effect of the harmonics, click on it to enlarge. This picture therefor only serves to show some (but important) effects of a non-ideal load.
As the two-port is modelled as a transmission line it is characterized by a characteristic impedance Z0 and a propagation constant γ. As the conductance value is low a constant value will not significantly detoriate the model behavior. Calculated is the response to a 1-0 pattern on each odd bit line and a 0-0 pattern on each even bit line. However, it does have moderately fast rising and falling edges where the sinewave passes through zero. This capacitance has a "negative feedback" effect on the MOSFET when it is undergoing a switching transition, and actually tries to prolong the switching transition, increasing switching losses! As the MOSFET switches, the driver has to source maximum current because it is trying to increase the gate-source voltage, but the Miller effect is trying to hold it constant! This can be via a mains isolating transformer, or a lower voltage power supply that provides isolation from the mains supply. Digital signals are defined in the time-domain where the voltage at the sampling frequency of the clock is important. When adding these delayed and reduced harmonics the square wave shows a typical RC shape with a slow rising edge. It also allows changes to be made to the gate-drive circuit without the risk of damaging the MOSFET if the change resulted in an unsuitable drive waveform. The Miller effect is also most noticeable in applications such as ours where the MOSFETs are operated at relatively high drain to source voltages.
It is the ability of a driver to overcome this effect that makes it win over a lesser gate drive circuit. Even if you can't check the waveforms with the full rated voltage applied to the MOSFETs, you should still check the waveforms at a lower voltage of 30 or 50 volts.
Power delivery can be further increased by interleaving up to six of these buck regulators using single wire current sharing without the need of any additional components. This proves that there are no unforseen oscillations, and gives some degree of confidence that the gate drive waveforms will not change greatly when the supply is increased further.
These losses increase with switching frequency and input voltage and limit maximum frequency operation, efficiency and power density.Gate Drive Losses a€“ Hard-switching topologies exhibit higher gate drive loss due to the Miller Charge dissipated within the gate drive circuitry. Body Diode Conduction a€“ High pulsating currents flow through the body diode of the low-side MOSFET as the high-side MOSFET gets turned on and off. The longer the body diode conducts, the higher the reverse-recovery losses and body diode conduction losses. The high switching frequency of this series also reduces the size of the external filtering components, improving power density while enabling fast dynamic response to line and load transients.

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