Dc ac converter for car,free birth chart horoscope within,tamil numerology compatibility calculator - Downloads 2016

Published : 15.03.2015 | Author : admin | Categories : Numerology 11
Attention: this ac to dc converter contains very high voltages that are deadly and you must be very careful!
This article was received from one of our visitors, please take into consideration that the presented information might not be correct. Recent Questionshow can an AVR get a generated sin wave by matlab,using serial interface and realize it using DAC?
Hi audioguru,I have decided to build the circuit with CD4047 together with CD4001 and IRFZ44.
Hi audioguru,you mention that the 12V feeding the ICs should have a 100ohm resistor in series and a 16V zener diode to ground at the ICs.
Converter 12 VDC to 220 VAC is a tool that can convert the DC voltage of 12 volts to 220 volts AC. It means a fues(protiction from short circut for 12 V DC)in case of any over load in the circut it self.
Hi,i really admire your good work there but is it a square wave or a sine wave stuff and if its a square wave how can it be converted into a sine wave?
IC CA3130 is a 15MHz BiMOS operational(8pin) amplifier with MOSFET inputs and CMOS output.Gate protected MOSFETs are used in the inputs so that the IC has very high input impedance.
You have mentioned IC CA3130 in this post, but I cant see it in the circuit schematic of the inverter.
Basically I have a bunch of stuff I scanvanged from old throw aways,,, even a flat screen I found in the dumpster! Application of microprocessors and DSP in high-performance power electronic systems has been a long term pursuing goal in development of control techniques for power converting systems [1]-[6]. Single-ended, half-bridge, or full-bridge PFC converters are all boost converters, from the point-of-view of control loop design they have the same dynamics. From the point-of-view of power circuit design, these three PFC converters have the same utilization factor, which result the processing power ratings are proportional to their number of switches. The half-bridge PFC converter has advantages of common-neutral in UPS applications and a minimal number of power switches is required. Regulations on line current harmonics have made power factor control a basic requirement for power electronic equipment [14].
Conventional PFC control schemes focus on the shaping of the line current in proportional to the voltage and therefore, a current loop controller with wide bandwidth is required.
In order to improve the dynamic response of the PFC boost converter, various feedback control schemes have been analyzed in [15].
One major design challenge in synthesizing a digital PFC controller is that we must make a compromise between the line current distortion and a fast response of the dc-link voltage regulation. The inner current loop controller is required to regulate the line current with a high sampling rate, usually from 10 to 20 kHz.
Voltage Control Loop (fs=6 kHz): This loop is used to compensate the instantaneous output voltage to track a sinusoidal 60 Hz reference.
Current Control Loop (fs=24 kHz): The current loop plays a most important role in the control of a PWM inverter for ac voltage regulation. Block diagram of the digital adaptive variable structure control scheme for AC voltage regulation.
The booster in a UPS system is used to convert the battery output voltage to a much more high dc-link voltage. The battery charger in the designed UPS system is symmetric common-neutral flyback converter. TMS320F2407A, in realizing all the required control functions for a single-phase on-line UPS. This design uses very fast Fairchild IGBT's that don't have internal diodes so I had to use some RURG8060 that I had on hand..
The following files are PDF's that can be printed on a laser jet printer and glossy paper and then ironed onto copper clad PCB material to make your own PCB.
Controller Top Side Mirrored and Tiled - The top side needs to be mirrored as it will be reversed when placed on the blank copper.
Originally developed to drive some huge surplus MOSFET H-Bridges I have above 350Khz which did require these power devices. The big yellow 7.5 uf caps are DC blocking caps for the primary side of the DC-AC converter. A semiconductor switch circuit is connected to a primary winding of a transformer having a secondary winding connected to a load. FIELD OF THE INVENTIONThe invention relates to a dc-ac converter (hereinafter referred to as inverter) for converting the dc voltage of such dc power supply as a power supply adapter and a battery of an electric apparatus into an ac voltage for driving a load. To achieve this voltage conversion we use a MC34161 rectifier as a voltage doubler at low input voltages and as a classic rectifier at high input voltages.
How the soil moisture sensor knows soil is wet or dry Hi orbital introduced in the mobile blockers that only have a chair surrounded. That circuit is not a purely a square wave as the presence of inductor and capacitor act as a filter. Hopefully, it i will be able to get the voltage and waveform that was required.Just to clarify something, the resistor value that was input to CD4047, can i use a potentiometer instead of fixed value so as i can adjust the frequency accordingly? I obtained a constant DC output for the cd4047 at pin 13 instead of a square waveform(Clock pulse). Circuits converter 12 volt DC to 220V AC in the figure below is an example of a simple converter circuit. Although this is not part of any professional dc ac converter it can be used quite effective on some home appliances.
If any needs help on the please contact me on me email address, I may get you 100% done without any problem. However, due to the complicated control functions required in a UPS system, most of the previous works were focused on the digital control of the PWM inverter for ac voltage regulation. Many research works have been carried out on the closed-loop regulation of PWM inverters using various feedback control schemes to achieve both good dynamic response and low harmonic distortion. The only difference is the effective voltage applied to the inductor due to a specified PWM duty. However, it also has disadvantages of higher voltage stress and need fast response balance control of the totem-pole capacitor bank. The main purpose of the PFC converter is to shape the input current to be linear proportional to its input voltage so that it behaves as a resistor. However, in order to minimize the current distortion resulted from the dc-link voltage regulation, a low-pass filter is required to smooth the double line frequency ripples in the dc-link voltage. Analog notch filter to eliminate measured output voltage ripples can achieve a better dynamic response compared with other approaches. The PFC controller consists of three sub-controllers: an inner current loop controller, an outer voltage loop controller, and an adaptive ripple estimator.
The outer voltage loop controller is used to regulate the dc-link voltage and at the same time to generate a current reference for the current loop. The desired closed-loop bandwidth (600 Hz) should be at least ten times of the reference frequency (60 Hz).
A proportional controller is used for the current regulation and a simple PI controller is used for the voltage regulation. This series is based on the C2xLP 16-bit, fixed-point, low-power DSP CPU, and is complemented with a wide range of on-chip peripherals and on-chip ROM or flash program memory, plus on-chip dual-access RAM (DARAM).
Experimental results show the designed 2 kVA UPS can reach very good dynamic responses both in utility interface and output voltage regulation. Because the gates of the 60N6S2 IGBT's are so easy to drive I just used UCC drivers and a gate drive transformer.
The semiconductor switch circuit has switches controlled by PWM to provide a controlled constant current. The dc-ac converter according to claim 1, wherein the switches of said semiconductor switch circuit are MOSFETs. The dc-ac converter according to claim 2, wherein said switch driving circuit has a logic circuit receiving said control signal and run-stop signal, said switch driving circuit adapted to form said switch drive signal based on the output of said logic circuit. The dc-ac converter according to claim 1, wherein said load is a cold cathode fluorescent light.
The controller IC according to claim 7, wherein said switch driving circuit has a logic circuit receiving said control signal and run-stop signal, said switch driving circuit adapted to form said switch drive signal based on the output of said logic circuit. The invention also relates to a controller IC for use with such inverter.BACKGROUND OF THE INVENTIONA cold cathode fluorescent light (CCFL) has been increasingly used as a backlight source of a liquid crystal display (LCD) monitor of a notebook PC and of an LCD for use with a TV set. Is it the same connection that you mention for the zener diode and resistor?if yes, but the diagram uses 47ohm as a resistor and not 100ohm so which one do i use? But i managed to get a square waveform at the pin 10 and 11 which both are inverted of one another at a frequency of 50Hz.
Dc to ac converter Circuits can be used to provide the source voltage at 220V AC lamp on emergency. Astable multivibrator in the circuit output converter 12 volt DC to AC 220 volt output above there are two paths are mutually 180 ° out of phase. Or is it available every where.I will like to know the total cost for the circuit components.
The total cost of this 12 Volts dc – 220 Volts ac is around 50$, depending on your location.
Microprocessor-based deadbeat control technique has been applied to the closed-loop regulation of PWM inverters.
Development of fast response control schemes for the PFC boost converter has become a technical pursuing goal in recent years [16]-[19]. Constant current with battery voltage profile control is adopted as the battery charging scheme.
In the inventive inverter, constant current control is performed by PWM operation of the switches of the semiconductor switch circuit.
Such CCFL has substantially the same high efficiency and long life as a usual hot cathode fluorescent light, without using a filament implemented in the hot cathode fluorescent light.The CCFL requires a high startup voltage and a high operating voltage. In the schematic universal-triac-control-with-optocoupler, the PNP transistor 2SB328 is shown as NPN. Now mine concerned is that how am i able to produce a 230Vrms output without any load connected at the output of transformer.
Also did you understand that the signal from your '555 must also have another signal 180 out of phase with it (two signals).
From my understanding, the dc capacitor will charge and discharge and thus able to make signal alternating.


You have an ICM7555 which is a low current Cmos 555 that has an output current of only a few milli-amps with a high voltage loss.
I think it has something to do with there tendancy toward non-linearity, so they are apt to produce more energy at various harmonics & spurious emittions.
According to the electronic forum, i had read that there were 2 capacitors required for non-polarities. I had changed a new cd4047 IC chip but the results are the same, do you know what are the reasons behind it?Thank you for your precious time.
The second output of each multivibrator is used to provide bias or triger to darlington transistor BC337 and TIP3055. Deadbeat control has been developed for the voltage regulation of the PWM inverter by employing a minor current loop and a major voltage loop. These control techniques break the bandwidth barrier of double line frequency by using sophisticated control techniques in elimination the influences of output voltage ripples. The charging profile is stored in the EEPROM of the UPS controller and can be reloaded when a new set of battery are installed.
The inverter cuts off electricity to the control circuit when putting the control circuit into a standby state if a run-stop signal gains a logical stop-state.
For example, a startup voltage of about 1000 V and an operating voltage of about 600 V are required. I hope that you are able to guide me on that schematics drawing on which part and how to modify it.As i was thinking whether can i change my rating of my transformer or can i modify the circuit in such that it will function as centre tapped transformer. If you don't use push-pull then you only need one transistor or you can parallel two of them but not like that. The TIP41 and TIP42 transistors need a base current of hundreds of milli-amps to switch 3A to produce 36VA.
It might be made with a cheating turns ratio to make up for a low output voltage when it is used for a step-down transformer. But according to the diagram, only the 220nF capacitor is required for the AC part but not for the 0.1uF capacitor which must have polarities.
With the difference multivibrator output pulses then the two pairs of Darlington transistors in the circuit of DC to AC converter will work on each in turn so that the transformers CT will receive two-way drive of the secondary side of transformers. However, deadbeat control scheme has the disadvantages of highly sensitive to parameter and load variations and requiring large peak-to-average ratio of control signals to achieve deadbeat effect.
All these control schemes are applied to the PFC boost converter and using analog controller or analog current-loop controller with microprocessor-based voltage-loop controller. This particular model isn't produced anymore as far as I know, but equivalent or better are available online. At the same time as the run-stop signal gaining the stop-state, switch drive signals enabling the switches of the semiconductor switch circuit are turned off. These high ac voltages are generated from a dc power supply of, for example, a notebook PC and a liquid crystal TV set, using an inverter.Conventionally, a Royer circuit has been used as an inverter for the CCFL.
Maybe it is what audioguru had stated about the losses.If i need to use centre tapped tranformer, i need to use 2 same npn transistors and not npn with pnp. DC to AC converter Circuits is built from power following a pulse from the astable multivibrator IC CD4047, darlington driver circuit transistor BC337 with TIP3055 then step-up converter is used as the primary transformer 220 volt and 12 volt CT. Converter using a transformer circuit output terminal CT with that used on the secondary side of the terminal 12 volt, 12 volt and CT. Thus, over-current can be prevented from flowing in the load when the control circuit is put into the standby state. The Royer circuit comprises a saturable magnetic core transformer and a control transistor, and is adapted to undergo a self-sustaining oscillation because of nonlinear permeability of the saturable magnetic core and nonlinear current gain characteristic of the control transistor. Converter Circuits can be supplied from an accumulator 12 volts to operate and provide 220 volts AC output voltage.
Then on the primary side can be selected as the output terminal 220 volt and 110 volt loads are supplied as required DC to AC converter circuit above.
I have posted a few that work in this forum.A CD4047 is an oscillator IC that uses one resistor and one capacitor. A complete circuit of components and a list of 12V DC to AC converter 220V in detail can be seen in the following figure. Hence, in order to maintain a constant input voltage to the Royer circuit, a regulator for supplying electric power to the Royer circuit is required.
It has two opposing square-wave outputs to drive two Mosfets that drive a center-tapped transformer. For this reason, besides the inverter utilizing a Royer circuit has low power inversion efficiency, it is difficult to miniaturize such inverter.A CCFL inverter having improved power conversion efficiency has been disclosed (see for example Japanese Patent Early Publication H10-50489). This inverter comprises a first semiconductor switch connected in series with the primary winding of a transformer, a second semiconductor switch and a capacitor which are connected in series with each other and in parallel with the primary winding, and a coupling capacitor is connected in series with the secondary winding of the transformer and with the load.
This inverter utilizes a transformer having a primary winding connected to the output terminal of the H bridge via a resonant capacitor connected in series with the primary winding.
Of the four semiconductor switches constituting the H bridge, a first set of two semiconductor switches establishes a current path in a first direction to the primary winding of the transformer and a second set of two semiconductor switches establishes a current path in a second direction to the primary winding.
By feeding the secondary current back to a control circuit for comparison of the voltage indicative of the current with a reference voltage, a control signal having a fixed pulse-width and controlled relative pulse position is generated.
The control signal is provided to the semiconductor switches of the H bridge to thereby regulate the power supplied to the load.
However, the gates of the semiconductor switches receiving the drive signals have capacitances, that prevent the semiconductor switches from being turned off instantly if the drive signals were stopped, thereby causing the current to continue to flow for a while. This current continues to flow until the electric charge on the capacitive gate of each semiconductor switch is completely discharged through a pull-down (or pull-up) resistor. 1 is a schematic diagram showing an overall arrangement of an inverter in accordance with the invention.FIG. 2 is a schematic diagram showing an internal structure of a controller IC for use in the inverter of FIG. 3 is a schematic diagram of a circuit that participates in startup and stopping operation of the inverter.FIG. 4 is a schematic diagram showing an output block along with a semiconductor switch circuit.FIG.
1.BEST MODE FOR CARRYING OUT THE INVENTIONReferring to the accompanying drawings, an inverter and a controller IC therefor in accordance with one embodiment of the invention will now be described in detail.
The inverter shown herein generates from a dc power supply an ac voltage for driving a load.Referring to FIG. 1, there is shown an overall arrangement of an inverter according to the invention that utilizes an insulated transformer and a full bridge switch circuit for carrying out PWM. 1, a first switch in the form of a P-type MOSFET (hereinafter referred to as PMOS) 101 and a second switch in the form of an N-type MOSFET (hereinafter referred to as NMOS) 102 constitute a first current path in a first direction from a dc power supply to the primary winding 105 of a transformer TR.
A third switch in the form of a PMOS 103 and a fourth switch in the form of NMOS 104 constitute a second current path in a second direction from the dc power supply to the primary winding 105 of the transformer TR. Each of these PMOSs 101 and 103 and NMOSs 102 and 104 have a body diode (or back gate diode). With these body diodes, current can be passed in the second direction opposite to the first. Additional diodes may be provided to fulfill the same function as the body diodes.The primary winding 105 of the transformer TR is supplied with a power supply voltage VCC from a dc power supply BAT through PMOSs 101 and 103 and NMOSs 102 and 104 to induce a high voltage across a secondary winding 106 of the transformer TR in accordance with the winding ratio of the primary to the secondary winding.
The induced high voltage is supplied to a cold cathode fluorescent light FL to turn it on.Capacitors 111–112 and resistors 117–118 are provided to detect the voltage impressed on the cold cathode fluorescent light FL and feed the detected voltage back to a controller IC 200.
Resistors 114–115 are provided to detect the current that flows through the cold cathode fluorescent light FL and feed it back to the controller IC 200.
The capacitance of the cold cathode fluorescent light FL also contributes to the resonance. A first pin 1P is a mode switching terminal for switching operational mode between PWM mode and intermittent operation mode (hereinafter referred to as burst mode). The first pin 1P is supplied with a duty signal DUTY for switching the operation mode and for determining the duty cycle ratio during the burst mode. A second pin 2P is a terminal (capacitive connection terminal) for connection with the capacitor 131 of a burst mode oscillator (BOSC). The second pin 2P is connected to the capacitor 131 to generate across the capacitor a triangular wave signal (i.e.
The triangular wave signal will hereinafter be referred to as burst triangular wave signal.A third pin 3P is a terminal for connection with a capacitor 132 to establish an oscillation frequency of a PWM mode oscillator (OSC). A fourth pin 4P is a terminal for connection with a resistor 133 for setting up a charge current to the third pin 3P. The fourth pin 4P has a potential RT, which causes a current to flow through the resistor 133 connected thereto in accord with the potential RT and the resistance of the resistor 133. The charge current setting resistor 134 connected to the sixth pin 6P is connected in parallel with the resistor 133 or disconnected therefrom, under the control of an internal circuit of the controller IC 200. The sixth pin 6P has a potential SRT, which equals either the ground potential GND or the potential RT of the fourth pin 4P.
A seventh pin 7P is a terminal for connection with a capacitor 135 for setting a timer latch.
The capacitor 135 when connected to the seventh pin 7P stores a charge, developing a voltage SCP in accord with the charge. The capacitor 135 determines the time limit of protective action to protect the internal circuit of the controller IC 200.A ninth pin 9P is an input terminal of a first error amplifier. The ninth pin 9P is fed, via a resistor 140, with a current detection signal (referred to as detection current) IS in accord with the current flowing through the cold cathode fluorescent light FL. The potential of the eighth pin 8P serves as feedback control voltage FB for the PWM control. In what follows the ground potential is taken as a reference for voltages unless otherwise stated.A tenth pin 10P is an input terminal of a second error amplifier.
The tenth pin 10P is fed, via a resistor 139, with a voltage detection signal (hereinafter referred to as detection voltage) VS in accord with the voltage impressed on the cold cathode fluorescent light FL. A signal STB is derived from a delayed startup signal ST by removing the noise therefrom by means of a resistor 143 and a capacitor 142, and is supplied to an eleventh pin 11P.
A twelfth pin 12P is a terminal for connection with a grounded capacitor 141 for setting slow-start time. A slow-start voltage SS gradually develops across the capacitor 141 during a startup.A thirteenth pin 13P is a synchronization terminal to be connected to another controller IC when the controller 200 is to be synchronized therewith.
A twentieth pin 20P is a power supply terminal for receiving the power supply voltage VCC.As shown in FIG. The frequency of the burst triangular wave signal BCT is set much lower than the frequency of the PWM triangular wave signal CT (i.e.


The dc voltage supplied to the first pin 1P (that is, analog duty signal DUTY) is compared with the burst triangular wave signal BCT in a comparator 221. The output of the comparator 221 is used to drive an NPN transistor (hereinafter referred to as NPN) 234 via an OR circuit 239. In a case where a digital (PWM) duty signal DUTY is supplied to the first pin 1P, a resistor is connected to the second pin 2P to output a predetermined burst voltage from the BOSC block 202.The logic block 203 is supplied with a PWM control signal, for example, to generate a switch drive signal in accord with a predetermined logic. An output block 204 generates gate drive signals P1, P2, N1, and N2, in accord with the switch drive signal received from the logic block 203, and supplies them to the respective gates of the PMOSs 101 and 103 and NMOSs 102 and 104.A slow start block 205 is started up by the output of a comparator 217 when the startup signal ST is supplied and the signal STB inputted to the comparator 217 is raised slowly by the capacitor 142 and resistor 143 above a reference voltage Vref6. The output of the comparator 217 resets a flip-flop (FF) circuit 242 via an OR circuit 243. As the start block 205 is started up, the slow-start voltage SS gradually rises, which is inputted to the PWM comparator 214 as a comparison input. Thus, at the time of startup, PWM control is executed by the slow-start voltage SS.It is noted that during a startup, the comparator 216 turns off an NMOS 246 via an OR circuit 247 when the input voltage to the comparator 216 exceeds a reference voltage Vref5. This causes the resistor 134 to be separated from the controller IC 200 and the frequency of the PWM triangular wave signal CT to be changed.
Under a steady state condition reached subsequent to a startup, a triangular wave signal CT is compared with the feedback voltage FB for automated control of the current flowing through the cold cathode fluorescent light FL at a preset level.Because the capacitor 136 is connected between the eighth pin 8P and the ninth pin 9P, the feedback voltage FB increases and decreases smoothly. This output is used to control a double collector type NPN 238 having one end connected to the constant current source I1. Since the collector of the NPN 238 is also connected to the pin 8P, the feedback voltage FB is also controlled by the detection voltage VS.
2.2 V) to turn on the NPN 234 via an AND circuit 244 and an OR circuit 239 when the voltage SS exceeds the reference voltage Vref8.
The NPN 234, when turned ON, causes a diode 232 to be reversely biased by a current source I2 and hence enables the first error amplifier 211 to perform its normal operation.
Thus, the NPN 234, diode 232, and the current source I2 constitute a control mode switching circuit for switching the control mode between burst control and pulse width control mode. 3 V), and inverts its output voltage when the feedback voltage FB exceeds the reference voltage Vref10. The outputs of the comparators 219 and 220 are inputted, along with the inverted output of the comparator 218, to a timer block 206 via an OR circuit 245. The output of this timer block 206 is supplied to the FF 242 to set it, and the Q output of which in turn disables the logic block 203.Next, referring to the timing diagrams shown in FIGS.
3–5, operation of the inverter, especially during startup, normal operation, and stopping operation, will now be described.
4 shows an exemplary circuit structure of the output block 204, along with a semiconductor switch circuit. 5 is a timing diagram useful in describing the operations.The output block 204 shown in FIG.
Each of the drive circuits 204-1–204-4 has a CMOS type inverting circuit consisting of a PMOS Qp and an NMOS Qn, and a pull-up or pull-down resistor Rp.
Symbols Cp represent virtual capacitances each formed between the gate and source of each of the semiconductor switches 101–104.
Each of the capacitances Cp is charged in accordance with the magnitude of the associated gate drive signal P1–N2, and is discharged via an associated one of the resistors Rp.When the controller IC 200 shown in FIG. 3 is supplied with the power supply voltage VCC, if the startup signal ST is pulled up to H level, a startup signal STB rises with a time constant determined by the resistance of the resistor 143 and the capacitance of the capacitor 142.
If the startup signal STB exceeds the reference voltage Vref6, the output of the comparator 217 is pulled down from H level to L level, thereby, removing standby conditions keeping the inverter in a standby (system-off) state and supplying the power supply voltage VCC to further sections of the controller IC 200.As the L level output of the comparator 217 is supplied to the start block 205 that includes a slow-start circuit, the constant-current source within the start block 205 is driven to supply constant current to the capacitor 141.
The capacitor 141 will be charged by the constant current, causing the slow-start voltage SS to rise. That is, slow-start begins in the startup.Thanks to a common circuit that consists of the constant current source I1 receiving the power supply voltage VCC and the NPNs 235 and 238, the feedback voltage FB to be supplied to one of the two (?)-input terminals of the PWM comparator 214 slowly rises to a high (H) level (maximum upper limit). The level of this feedback voltage FB is constrained to this constant value determined by the PNP 231 and the reference voltage Vref1.The slowly rising slow-start voltage SS is compared with the triangular wave signal CT in the PWM comparator 214, whereby a PWM control signal PWM1 is outputted from the PWM comparator 214 in accord with the magnitude of the slow-start voltage SS. Incidentally, the PWM comparator 214 outputs a PWM control signal PWM1 of H level when the triangular wave signal CT has a level lower than the slow-start voltage SS and the feedback voltage FB.
On the other hand, since the output of the inversion circuit 249 has H level, the PWM control signal PWM1 is outputted as PWM control signal PWM2 after it has passed through the AND circuit 248. Therefore, although the initial feedback voltage FB has the upper limit level, the inventive inverter, unlike conventional inverters, will not initially impress an excessive output voltage Vo (as high as 2000–2500 V, for example) on the cold cathode fluorescent light FL.
Moreover, since there can be no inrushing current that accompanies such excessive output voltage Vo, the cold cathode fluorescent light FL and the major circuit components (e.g. As the NPN 235 or NPN 238 is controlled, the feedback voltage FB begins to fall from the upper limit level.When the output voltage Vo reaches the startup voltage (about 1000 V), the output current Io begins to flow, turning on the cold cathode fluorescent light FL, which in turn causes the output voltage Vo to fall to a predetermined operating voltage (about 600 V). The output current Io gradually grows up, while the output voltage Vo remains at the substantially constant operating voltage. As the output voltage Vo or the output current Io grows larger, causing the NPN 235 or 238 to be controlled, the feedback voltage FB is gradually lowered from the upper limit level by the feedback action of the capacitors 136 and 137.As the slow-start voltage SS rises, the output current Io increases and the feedback voltage FB decreases. When the feedback voltage FB becomes equal to the slow-start voltage SS, the PWM comparator 214 begins to compare the PWM triangular wave signal CT with the feedback voltage FB in place of the slow-start voltage SS that has been so far compared with the PWM triangular wave signal CT. The time required for the slow start is fairly long, since it takes time to start up the disabled cold cathode fluorescent light FL.The output current Io is controlled to remain at a predetermined constant level determined by the reference voltage Vref2. The luminance of the cold cathode fluorescent light FL is determined by the magnitude of the current flowing through it. Hence, in order to maintain this current, a substantially constant operating voltage must be applied to the cold cathode fluorescent light FL. Thus, in order to turn on the cold cathode fluorescent light FL, the output voltage Vo is brought to a high level during a startup, but it can be lowered to a low operating voltage once the fluorescent light FL is turned on. Hence, the level of the feedback voltage FB in the steady state that follows the slow start is determined based on the magnitude of the output current Io.As shown in FIG. 5, since the startup signal ST has H level, the gate drive signals P1–N2 are formed based on the PWM control signal PWM1 and the internal clock given by the OSC block 201, which drive the semiconductor switch circuit. The current that flows through the primary winding 105 of the transformer TR (which is here expressed as load current Io) flows alternately in the first and second directions.The current Io flows in the first direction when the gate drive signal P1 is L level and the gate drive signal N1 is H level. That is, the current Io in the first direction starts to flow when the gate drive signal N1 is pulled to H level, and increases while the gate drive signal N1 is H level. As the gate drive signal N1 is pulled down from H level to L level, the current Io flowing in the first direction starts to decrease, releasing the energy stored in the primary winding 105.The current Io starts to flow in the second direction when the gate drive signal N2 is pulled up to H level and increases while the gate drive signal N2 remains H level. As the gate drive signal N2 is pulled down from H level to L level, the current Io flowing in the second direction starts to decrease, releasing the energy stored in the primary winding 105. In this way, a current Io having a magnitude determined by the PWM control signal PWM1 flows through the primary winding 105 in the opposite directions alternately, effecting the inverter operation. Toff is a period provided to prevent penetration current.Each of the switches 101–104 of this semiconductor switch circuit is switched on and off as shown in FIG. The NMOS 102 turns on at every other apex of the triangular wave signal CT on one side thereof with respect to the average of the triangular wave signal CT and remains so until the immediately subsequent triangular wave signal CT and the feedback signal FB become equal in magnitude.
The PMOS 101 is turned on a first predetermined time before the NMOS 102 is turned on and remains so until the triangular wave signal CT reaches the apex on the other side immediately after the NMOS 102 turns off.
The NMOS 104 turns on at every other apex of the triangular wave signal CT, the apex being different from said every other apex associated with the NMOS 102, and remains so until the immediately subsequent triangular wave signal CT and the feedback signal FB become equal in magnitude. The PMOS 103 turns on a second predetermined time before the NMOS 104 turns on, under the condition that the NMOS 102 is turned off and the PMOS 101 is turned on.
The PMOS 103 remains turned on until the triangular wave signal CT reaches its apex on the other side thereof immediately after the NMOS 104 turns off.
The first and second predetermined times are respectively set to lengths such that either one of the PMOSs 101 and 103 is switched on.To put the inverter operating into a standby state, the startup signal ST is pulled down from H level to L level. Since this change in level of the startup signal ST is made at an arbitrary point of time, the pulling is not synchronized with PWM control.In the standby mode, electricity to the controller IC 200 except for portions thereof that must be kept energized in standby state is cut off.
Power is then still supplied to the PMOSs 101 and 103 and NMOSs 102 and 104.Let us now suppose that the gate drive signal N1 is at H level and the current Io is flowing in the first direction at time t1, when the startup signal ST is pulled down to L level.
It takes some time before the output of the comparator 217 is inverted following the change in the startup signal ST. However, this does not matter, since the startup of the comparator 217 is initiated by the inversion.As the startup signal ST is lowered to L level, a system-off signal SYSTEM OFF will be generated. Because of the system-off signal SYSTEM OFF, electricity is cut off to the controller IC 200 except for the portions thereof (e.g.
However, it takes some time (system-off time) on the order of from several dozen microseconds to several hundred microseconds after t1, before the voltages supplied to various components (for example, PWM comparator 214, logic block 203, and output block 204) diminish to stop these components.In this invention, the AND circuit 248 is closed at time t1 when the startup signal ST is lowered to L level, so that the output PWM2 of the AND circuit 248 is then promptly pulled down from H level to L level. This causes the level of the signal supplied from the logic block 203 to the inversion circuit of the drive circuit 204-2 is inverted from L level to H level, and causes PMOS Qp (which has been turned on) to be turned off and NMOS Qn (which has been turned off) to be turned on.As a result, the charge stored in the capacitance Cp of the NMOS 102 is discharged through NMOS Qn without passing through the resistor Rp.
The time required for the discharge (referred to as discharge time) is extremely short, which is, for example, about 500 ns.
Consequently, the current Io that has been increasing in the first direction up to t1 starts decreasing at the moment when the NMOS 102 turns off at t1.After the system-off time has passed, both the PMOS Qp and NMOS Qn of the drive circuit 204-2 turn off.
Since this system-off time (ranging from several 10 to several 100 micro-seconds) is extremely short as compared to the discharge time (i.e. However, in the conventional inverter, unlike the inventive inverter, PWM control signal PWM is not controlled by a startup signal ST.Referring to FIGS.
4 and 5, one may see behaviors of drive circuit 204-2 and NMOS 102 of the conventional inverter making a transition to a standby state. As a result of cut off of power, the level of the power supply voltage VCC of the drive circuit 204-2 gradually falls. As a consequence, the PMOS Qp of the drive circuit 204-2 remains turned on for a while, and then turned off subsequently. The NMOS Qn of the drive circuit 204-2 remains turned off all the time.In this case, since the charge of the capacitances Cp only discharges through a resistor Rp, the gate drive signal N1 decreases slowly according to the time constant Cp*Rp, as shown in FIG. The NMOS 102 will turn off only if the gate drive signal N1 enabling the NMOS 102 lowers below the threshold value voltage at t2.
The same is true also in other drive circuits.In the conventional inverter, therefore, the load current Io continues to increase even after t1, until the NMOS 102 turns off at t2 as shown in FIG. The magnitude of the load current Io then reaches a magnitude which is a few times (4 times in the example shown herein) the ordinary load current, though the load current is a single pulse.As described above, in the present invention, a system-off signal SYSTEM OFF is generated in response to a startup signal ST when the inverter is put into a standby state, whereby the SYSTEM OFF signal stops the electric power to those components that need not be powered in the standby state, and at the same time the switch drive signals outputted from the switch driving circuit of the output block 204 are turned off.
Thus, instead of providing the AND circuit 248 and inversion circuit 249, the startup signal ST may be directly inputted to the logic block 203 or the output block 204 to achieve the same result.INDUSTRIAL APPLICABILITYAs described above, the inventive dc-ac converter and controller IC therefor are suitable for use with a backlight source of a liquid crystal display that requires a high ac voltage to be obtained from a low dc voltage source.



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