Over the past several years we’ve seen multiple companies tackle the problem of finding a new memory standard to replace NAND flash.
Samsung Electronics have developed VRRAM technology for replacing memory tech to Nand Flash.
ReRAM is interesting stuff, but phase-change memory appears to be pulling ahead in terms of total implementation and deployment. So will there ever be a PCI Express V4 or will a whole new interface be designed for these super fast SSDs? It seems like a lot of change is needed to support the latest hardware and the market seems stuck on portable devices.
The majority of SSD systems don’t sell for less than $1000 unless they use cache drives, which still tend to carry significant premiums.
Oh this got memcache and read db works written all over it… or if they put them up like a special ram stick you could use it as a huge apc mempool.
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As compared to the common flash memory being used nowadays for several applications, the phase-change memory will surely have a larger capacity in terms of storage.
The technology behind phase-change is based on materials that change from a shapeless structure to a crystalline structure once an electric pulse passes through it.
Another problem with the ubiquitous flash memory is that it starts to encounter problems when it gets smaller than 20 nanometers.
The research team working on the phase-change memory is headed by Xilin Zhou of the Shanghai Institute of Microsystem and Information Technology at the University of the Chinese Academy of Sciences in Beijing, China. Phase change materials can switch between two forms depending on how quickly they're cooled. This difference has been exploited to create a type of storage called phase change memory that's as fast as standard RAM but retains its contents between power cycles. The efforts started out with a simple arrangement of resistors and phase change bits that operated like a logic gate, allowing AND, OR, and NOT operations. Phase change memory has been researched for a number of years, and commercial products have even been developed. To create memory based on this setup, a small amount of the alloy is coupled with an electrical heating element that can raise the temperatures enough to melt the alloy and control how rapidly it cools.
Last year, however, researchers showed that phase change memory could also be used to create logic gates, the basic functional units of a modern computer.
The new work, performed by a collaboration between researchers in Cambridge UK and Singapore, attempts to both simplify and speed up the operation of these phase change circuits. The authors consider their low-heat pulse to be binary zero and the high-heat version to be binary 1.
Although the paper's authors are understandably enthusiastic, there are some real barriers between this proof of concept and anything useful. The material on this site may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of Conde Nast. IBM has demonstrated a new type of memory technology that the company believes could one day be a replacement for NAND flash.
That’s a huge step back from Micron, which actually had a shipping solution you could buy. I already posted them once, look for my reply to DOSGuy, since copying and pasting didn’t work.
I compared the latest commercially available PCM (well, the most recently-available) against the latest NAND. Great article, does this mean that the shorter the delay time the more data you can push through a CPU as there might be a lot of unused clock cycles using our current storage devices. The purpose of an L1 cache is to tell the CPU where information is stored in main memory (avoiding the need to search that memory pool). We will undoubtedly replace DRAM one day with something, but there will always be a tradeoff.
L3 bigger and slower more like a buffer for data that has just been fetched, than it is the rest of the system. I think economies of scale (not the underlying science) will be the driving factor that decides when something disruptive appears in your iThing or on the shelf for you at BestBuy.
Faster data transfer speeds up application performance when the application depends on reading data out of a slow storage medium. Yeh this is exactly what I assumed I just couldn’t explain it as well as you, thanks for the excellent replies! I really can’t wait for heterogeneous computing to take off so we can have processors specifically designed to deal with certain task functions.
Because PCM have simplier architechture than MLC-type of Nand Flash will the manufacturing costs be reduced compaired to MLC Nand Flash. We always read about these new technologies but we almost never seem to see them on the shelves. The chalcogenic compound is surrounded by two electrodes along with a wire to the compound. When melted it loses all crystalline structure, and rapid cooling below glass transition temperature causes the material to be locked into its amorphous phase.
The above figure shows the device read resistance resultingfrom application of the programming current pulse amplitude.
By pre-organizing atoms in a bit of phase-change memory, information can be written in less than one nanosecond, the fastest for such memory. Phase-change memory stores information based on the organization of atoms in a material, often a mixture of germanium, antimony, and tellurium (Ge2Sb2Te5 or GST). Phase-change memory could one day replace flash memory in our cellphones, just as Samsung briefly tried in a commercial smartphone.
That makes phase-change memory an intriguing candidate to replace the volatile DRAM that powers our computers.
Elliott and his colleagues have boosted the crystallization time, and thus the write speed, of a stable PRAM bit. Computer models of the material show that the constant low voltage causes tiny seed crystals to form, basically “priming” the atoms for complete crystallization. Most researchers have tried to improve the switching speed of phase change memory by randomly inserting metals into GST, says Robert Simpson, at the Institute of Photonic Sciences in Spain.

Eric Pop, of the University of Illinois, Urbana-Champaign, is excited to see the speed limits of phase-change memory bits, but wonders if the extra power needed to maintain the low priming voltage would influence the speed and energy consumption of a chip containing many phase-change bits.
This story was updated on June 25, 2012 to reflect the fact that GST is a glassy material, not a metal. Despite NAND’s superior performance characteristics, it faces long-term scaling issues. I guess I never really considered how much of a difference there is between the different levels of the memory hierarchy.
Imagine a ram pool of 512gb on the ram lane with those latencies used for apc or any other memcaching… this can’t come soon enough !!!
When the material is in its amorphous state, it has high electrical resistance and inversely, it has low resistance when the material is in its crystalline state.
Interestingly, a phase-memory device allows more memory to be squeezed in at less than 10 nanometers which is one of the most important factors to consider.
As of the moment, the team is investigating the endurance or reversible electrical switching of the phase-change memory cell with MLS capacity.
Cool them quickly and you get an amorphous form, which provides significant resistance to the flow of electrons.
But a new paper shows that by carefully controlling how the phase change bits are set in the first place, it's possible to have a single bit perform different logic operations, acting as a NOT, NOR, or NAND gate.
It relies on the fact that some chemicals (typically alloys of Ge2Sb2Te5) change their electrical conductivity depending on whether they adopt a crystalline or amorphous form. Although this process might sound slow, actual implementations are nearly as fast as the RAM in your computer.
The original work involved hooking up individual phase change memory bits with resistors in precise combinations. The idea behind the new work is that a low level of heating can set the hardware in a state that makes it more prone to switch, speeding up the process of switching between binary 1 and 0. They then show that the value left in the bit after various combinations of pulses makes the single bit the equivalent of binary NOR gate (low-low doesn't flip it to 0; everything else does). The authors suggest that it may be a solution to increase computers' ability to scale, but there would clearly be a fair bit of control logic involved in arranging to send the right combinations of pulses to the individual bits. The company’s Theseus Project (conducted in cooperation with the University of Patras in Greece) is the first attempt to combine phase change memory, conventional NAND, and DRAM on a single controller.
The ITRS takes the position that with NAND densities increasing thanks to 3D NAND (even with the issues that it’s having), the need for replacement memories will likely push off widespread deployment. You asked if we could make PCM that stores more than one bit of information per cell (equivalent to SLC NAND). So getting the data their faster means your freeing up processing by creating denser data flows…. In order to be as fast and as high-bandwidth as it is, L1 is very expensive to manufacture. Making the L1 huge would make it extremely expensive and it would eat an enormous amount of die space.
And if you’re running heavy workloads with lots of simultaneous data reads and writes, lower latencies and faster transfer rates can have a huge impact on total performance. It’s really great when we see true evolution in the medium the technology is based apon instead of incremental updates.
It does not make economic sense to them, so if they want to keep the costs at current levels they will artificially reduce the speeds via firmware or some other way.
This phase is very stable near room temperature, but the rate of nucleation and growth of crystallites increases exponentially as the melting temperature is approached. Startingin the set condition, moving from left to right, the device continues toremain in SET state as the amplitude is increased. With write speeds comparable to the memory that powers our computers, phase change memory could one day help computers boot up instantly.
A voltage pulse heats the metal and disordered atoms in the crystal rearrange into an ordered crystal. But a computer that boots up instantly using PRAM is still a long way off, partly because the materials can’t be switched from disordered to ordered, or written quickly enough.
Learning how to create crystal seeds through simulations and then demonstrating how these seeds speed crystallization in a device is a more scientific approach to developing new memory materials, he adds. She writes about chemistry, physics and technology and holds a PhD in chemistry from Washington University in St. Just like the IBM demonstration of earlier this year, the HGST hardware was based on Micron phase change memory — and Micron is taking a strategic break from that business segment. The biggest problem that we’re facing right now is the hard limit of maximal memory per module and its physical size. The new technology consists of 50 aluminum atoms bound to 50 atoms of antimony and is considered as a very promising discovery which could dramatically change the way memory devices will be made in the near future. Smart modern consumers would surely prefer something smaller in size but bigger in capacity at the same time. They are also looking forward to having it out in the market as soon as everything has been finalized. But some researchers are now experimenting with the idea of building processors out of the technology. To control this, all you need to do is control how rapidly the material is cooled from a molten state. And once the bit is written, the material remains stable without any additional power requirements, which makes phase change memory a great option for situations where data doesn't change often but power is a concern. Although the approach worked, the operations were much slower than what we'd need for a functional computer. Logical operations can then be performed using combinations of pulses of this low heat and the high heat normally used to flip the bit. Here, the fast switching allows state changes in as little as 900 picoseconds—much closer to the speed of modern processors. The authors also fuss about the fast switching they've enabled, but some of the logical operations require a separation between pulses that stretches out the time involved considerably. And sometimes it's just important to put a technology out there; someone else may eventually figure out how to do something useful with it, even if it takes years.
Note that the PSS solution (that’s the PCM card) completes the overwhelming majority of its requests in under 500 microseconds.

I would prefer to see a NAND replacement sooner rather than later, even if consumer applications take 5-10 years to follow storage server deployments.
Numonyx apparently has shipped some 512Mbit to specific customers, so that may be the highest density in current production. I just don’t really understand how faster data transfers results in greater application performance? The wire is heated through Joule heating whereby due to high resistance of the heating element, when current passes through it, it heats up a high temperature very quickly. To switch the memory element back to its conductive state, the material is heated to a temperature between the glass transition temperature and the melting temperature, causing nucleation and crystal growth to rapidly occur over a period of several nanoseconds.
To program the device, a pulse of sufficient voltageis applied to drive the device into a high conduction “dynamic onstate”.
Further increase inthe pulse amplitude begins to reset the device with still further increaseresetting the device to a standard amorphous resistance.
Restoring the disordered arrangement by melting the glassy material erases the information.
And like flash, PRAM is nonvolatile, meaning that it retains its information even when a device is powered off. Most phase-change materials crystallize slower than the 1-10 nanoseconds it takes to write a bit of DRAM.
The scientists sandwiched a 50nm-wide cylinder of GST between two titanium electrodes and applied 0.3V of potential across the material. Typical random access read latency for consumer NAND is 0.1ms, or roughly 100 microseconds. Reproduction in whole or in part in any form or medium without express written permission of Ziff Davis, LLC.
Once cooled, these two forms remain stable, locking the differences in conduction in place. In fact, that announcement appears to be the only thing they’ve said on the topic at all. 0 to 1 == high to low res.== amorphous to crystal == small current 1 to 0 == low to high res. Beginningagain with a device initially in the RESET state, low amplitude pulses atvoltages less than Vth do not set the device.
A computer reads each bit by detecting the lower electrical resistance of the ordered crystal.
And materials that crystallize faster at PRAM operating temperatures tend to naturally organize at lower temperatures too, says Stephen Elliott of the University of Cambridge. A 500-picosecond burst of 1V electrical potential triggered the crystallization, which is about 10 times faster than the best speed using a germanium-tellurium material. HGST is claiming access latencies almost two orders of magnitude smaller than the fastest SLC NAND flash you can buy.The accesses are so fast, in point of fact, that HGST had to rearchitect the entire PCI Express bus to stress test the phase change memory. With write latencies that are merely competitive with NAND flash, the focus will be on read accesses, where PCM can offer performance that’s within several orders of magnitude of main memory. Thus, a single piece of hardware can handle various logical operations depending on the input it's given.
Phase change memory works by rapidly heating chalcogenide glass, shifting it between its crystalline and amorphous state.
Once Vth is surpassed, thedevice switches to the dynamic on state and programmed resistance isdramatically reduced as crystallization of the material is achieved.Further increase in programming current further crystallizes thematerial, which drops the resistance to a minimum value. The company has published an eight-page whitepaper detailing its efforts — essentially it started with the Non Volatile Memory Express (NVMe) protocol, then rearchitected it to strip out all unnecessary communication. In its amorphous state (read as a binary 0), the structure has very high resistance, while in its crystalline state (binary 1) resistance is quite low. Micron gave notice earlier this year that it was cancelling all of its PCM production and pulling out of the industry.
The finalprogrammed state of the device is determined by the current amplitudeand the pulse duration in the dynamic on state.
As theprogramming pulse amplitude is increased further, resetting again isexhibited as in the case above.
According to HGST, strict performance criteria that actually leverage real-world test scenarios show NAND flash topping out at roughly 13,000 IOPS rather than the 90,000+ typically claimed by high-end hardware.
While it left open the door to revisiting the memory tech at some point in the future, it indicated that the superior scaling of 3D NAND was a better option (despite the numerous problems identified with that technology in the short term). The reciprocal slope ofthe I?V curve in the dynamic on state is the series device resistance.
The company claims this is limited by roughly 70 microseconds of read latency.By rearchitecting the bus protocol into what HGST calls DC Express, it was able to boost performance from 13,000 IOPS to 700,000 IOPS on the same material.
A year ago, I thought ReRAM was the odds-on favorite for an eventual NAND replacement, but I’ve got to say that the recent advances in phase change memory have me wondering if its not the better candidate. Importantly, the right side of the curveexhibits direct overwrite capability, where a particular resistance valuecan be obtained from a programming pulse, irrespective of the priorstate of the material.
100x better read performance and equivalent write performance is unquestionably good enough to carve its own niche, assuming issues of yield and density can be ironed out. Even so, NAND flash has enormous economies of scale and billions invested in fab plants across the world.
The small current raises the temperature above the crystallization and lets it slowly to keep it in that state.A larger current is used to change the state from a 1 to a 0.
The slope of the right side of the curve is the devicedesign parameter and can be adjusted to enable a multi? state memorycell. What IBM has done with Theseus is to incorporate a small amount of PCM into a hybrid structure where its ultra-low-latency characteristics can be effectively leveraged.This chart shows the various areas where IBM believes phase change memory could be useful. This is done by melting the crystalline state and quickly cooling it to leave it in the amorphous state. Note that in many cases, the PCM is being integrated either as a cache solution or as an additional tier of storage between NAND and DRAM, just as NAND is often integrated between DRAM and a conventional hard drive. Project Theseus is an aggregate controller featuring what appears to be 2.8GB of PCM (36 128Mbit cells per card, 5 cards total).

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